Switching techniques in data-acquisition systems for future experiments

An overview of the current state of development of parallel event-building techniques is given, with emphasis of future applications in the high-rate experiments proposed at the Large Hadron Collider (LHC). The paper describes the ain architectural options in parallel event builders, the proposed event-building architectures for LHC experiments, and the use of standard net- working protocols for event building and their limitations. The main issues around the potential use of circuit switching, message switching and packet switching are examined. Results from various laboratory demonstrator systems are presented

LHC1: a semiconductor pixel detector readout chip with internal, tunable delay providing a binary pattern of selected events

The Omega3/LHCl pixel detector readout chip comprises a matrix of 128 X 16 readout cells of 50 mu m X 500 mu m and peripheral functions with 4 distinct modes of initialization and operation, together more than 800 000 transistors. Each cell contains a complete chain of amplifier, discriminator with adjustable threshold and fast-OR output, a globally adjustable delay with local fine-tuning, coincidence logic and memory. Every cell can be individually addressed for electrical test and masking, First results have been obtained from electrical tests of a chip without detector as well as from source measurements, The electronic noise without detector is similar to 100 e(-) rms. The lowest threshold setting is close to 2000 e(-) and non-uniformity has been measured to be better than 450 e(-) rms at 5000 e(-) threshold. A timewalk of < 10 ns and a precision of < 6 ns rms on a delay of 2 mu s have been measured. The results may be improved by further optimization